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The HMC704 has been designed for the best phase noise and lowest spurious content possible in an integrated synthesizer. Fabricated in a SiGe BiCMOS process, this Fractional-N frequency synthesizer consists of a very low noise digital phase detector, VCO divider, reference divider and a precision controlled charge pump. Ultra low in-close phase noise and low spurious allows wide loop bandwidths for faster frequency hopping and low micro-phonics. Exact frequency mode with 24-bit fractional modulator provides the ability to generate fractional frequencies with zero frequency error, an important feature for Digital Pre-Distortion systems. The serial interface offers read back capability and is compatible with a wide variety of protocols. Rochester Electronics has partnered with Analog Devices to offer continuity of supply for this product which has now become EOL at Analog Devices. Please contact adirf@rocelec.com for ordering support for this EOL product. Applications Microwave Point-to-Point Radios Base Stations for Mobile Radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANs, WiMAX Communications Test Equipment CATV Equipment Automotive

IC INTEGER-N/FRACTIONAL 24QFN

IC FRACT-N PLL W/SWEEPR 48LFCSP

IC JITTER ATTENUATOR 68LFCSP

The HMC7043B, which is a revised version of the HMC7043 , is a high-performance clock buffer for the distribution of ultra-low phase noise references for high-speed data converters with either parallel or serial (JESD204B/C type) interfaces. The HMC7043B is designed to meet the requirements of multicarrier GSM and LTE base station designs, and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs. The HMC7043B provides 14 low noise and configurable outputs to offer flexibility in interfacing with many different components in a base transceiver station (BTS) system, such as data converters, local oscillators, transmit/receive modules, field programmable gate arrays (FPGAs), and digital front-end application-specific integrated circuits (ASICs). The HMC7043B can generate up to seven DCLK and SYSREF clock pairs per the JESD204B interface requirements. The system designer can generate a lower number of DCLK and SYSREF pairs, and configure the remaining output signal paths for independent phase and frequency. Both the DCLK and SYSREF clock outputs can be configured to support different signaling standards, including CML, LVDS, LVPECL, and low voltage complementary metal-oxide semiconductor (LVCMOS), and different bias conditions to adjust for varying board insertion losses. One of the unique features of the HMC7043B is the independent flexible phase management of each of the 14 channels. All 14 channels feature both frequency and phase adjustment. The outputs can also be programmed for 50 Ω or 100 Ω internal and external termination options. The HMC7043B device features an RF SYNC feature that synchronizes multiple HMC7043B devices deterministically, that is, ensures that all clock outputs start with the same edge. This operation is achieved by rephasing the nested HMC7043B or SYSREF control unit/divider, deterministically, and then restarting the output dividers with this new phase. The HMC7043B is offered in a 48-lead, 7 mm × 7 mm LFCSP package with an exposed pad connected to ground. APPLICATIONS JESD204B and JESD204C clock generation Cellular infrastructure (multicarrier global system for mobile communications/GSM, long-term evolution/LTE, wideband Code-Division Multiple Access/W-CDMA) Data converter clocking Phase array reference distribution Microwave baseband cards

The HMC7044B, which is the revised version of the HMC7044 , is a high performance, dual loop, integer N jitter attenuator capable of performing reference selection and generation of ultra-low phase noise frequencies for high-speed data converters with either parallel or serial (JESD204B and JESD204C type) interfaces. In the HMC7044B, the phase alignment of the outputs on edge cases such as temperature and supply voltage is improved. The HMC7044B features two integer mode PLLs and overlapping onchip VCOs that are SPI-selectable with wide tuning ranges around 2.5 GHz and 3 GHz, respectively. The device is designed to meet the requirements of GSM and LTE base station designs, and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs. The HMC7044B provides 14 low noise and configurable outputs to offer flexibility in interfacing with many different components including data converters, field-programmable gate arrays (FPGAs), and mixer local oscillators (LOs). The DCLK and SYSREF clock outputs of the HMC7044B can be configured to support signaling standards, such as CML, LVDS, LVPECL, and LVCMOS, and different bias settings to offset varying board insertion losses. APPLICATIONS JESD204B and JESD204C clock generation Cellular infrastructure (multicarrier GSM, LTE, W-CDMA) Data converter clocking Microwave baseband cards Phase array reference distribution

IC INTEGER-N/FRACTIONAL 24QFN

IC JITTER ATTENUATOR 68LFCSP

IC CLOCK BUFFER 48LFCSP