Alliance Memory, Inc.United States
IC DRAM 4GBIT PARALLEL 96FBGA
4Gb LPDDR3 SDRAM, 256Mx16 bits, 1.35V supply, 96-ball FBGA package, commercial temp 0 to +95°C, supports 1600/1866Mbps, lead-free and halogen-free.Checked against the datasheet
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Technical parameters
Key specs
Memory typeDRAM
Memory size4 Gbit
InterfaceParallel
Supply voltage75 mV ~ 1.5 VVDDQ = 1.35V (1.283V to 1.45V)
Clock frequency800 MHzMax
Datasheet-verified parameters
21 items| Parameter | Value and test conditions | Source |
|---|---|---|
| Memory Type | LPDDR3 SDRAM | |
| Density | 4G bits (256Mx16) | |
| Interface | x16 | |
| Supply Voltage | VDD, VDDQ = 1.35V (1.283V to 1.45V); Backward compatible to 1.5V ± 0.075V | |
| Max Clock Frequency | 800 MHz | |
| Package | 96-ball FBGA |
All parameters (19)
| Power | |
|---|---|
| Voltage - Supply | 1.283V ~ 1.45V |
| AC and DC characteristics | |
| Clock Frequency | 800 MHz |
| Environment and package | |
| Memory Size | 4Gbit |
| Mounting Type | Surface Mount |
| Operating Temperature | 0°C~95°C(TC) |
| Package | Tray |
| Package / Case | 96-TFBGA |
| Supplier Device Package | 96-FBGA (13.5x9) |
| Other | |
| Access Time | 20 ns |
| Base Product Number | AS4C256 |
| Memory Format | DRAM |
| Memory Interface | Parallel |
| Memory Organization | 256M x 16 |
| Memory Type | Volatile |
| Mfr | Alliance Memory, Inc. |
| Product Status | Obsolete |
| Series | - |
| Technology | SDRAM - DDR3L |
| Write Cycle Time - Word, Page | 15ns |
Pinout and package
Package96-ball FBGA
| Pin | Name | Function | Source |
|---|---|---|---|
| A0 - A14 | Address Inputs: Provided the row address for Active commands and the column address for Read / Write commands to select one location out of the memory array in the respective bank. (A10/AP and A12/BC have additional functions, see below) The address inputs also provide the op-code during Mode | ||
| A10 / AP | Autoprecharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH:Autoprecharge; LOW: No Autoprecharge) A10 is sampled during a Precharge command to determine whether the Precharge applies to one | ||
| A12 / BC# | Burst Chop: A12 is sampled during Read and Write commands to determine if burst chop(on-the-fly) will be performed. (HIGH: no burst chop, LOW: burst chopped). See command truth table for details. | ||
| BA0 - BA2 | Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines which mode register is to be accessed during a MRS cycle. | ||
| CK, CK# | Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output (read) data is referenced to the crossings of CK and CK#. | ||
| CKE | Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (Row Active in any bank). CKE is asynchronous for self refresh | ||
| CS# | Chip Select: All commands are masked when CS# is registered HIGH. CS# provides for external Rank selection on systems with multiple Ranks. CS# is considered part of the command code. | ||
| DM (DMU), (DML) | Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS#. | ||
| DQ | Data Input/ Output: Bi-directional data bus. | ||
| DQSL, DQSL# DQSU, DQ | Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. For the x16, DQSL corresponds to the data on DQL0-DQL7; DQSU corresponds to the data on DQU0-DQU7. The data strobe DQSL and DQSU are paired with differential signals DQSL# and DQSU#, res | ||
| NC | No Connect: No internal electrical connection is present. | ||
| ODT | On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS# and DM/TDQS, NU/TDQS# (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 configurations. The ODT pin will be ignored if the | ||
| RAS#, CAS#, WE# | Command Inputs: RAS#, CAS# and WE# (along with CS#) define the command being entered. | ||
| RESET# | Active Low Asynchronous Reset: Reset is active when RESET# is LOW, and inactive when RESET# is HIGH. RESET# must be HIGH during normal operation. RESET# is a CMOS rail to rail signal with DC high and low at 80% and 20% of VDD, i.e. 1.20V for DC high and 0.30V for DC low. | ||
| VDD | Power Supply: 1.35V, 1.283 - 1.45V operational; compatible to 1.5+/- 0.075V operation. | ||
| VDDQ | DQ | power supply: 1.35V, 1.283 - 1.45V operational; compatible to 1.5+/- 0.075V operation. | |
| VREFCA | Reference Voltage for CA | ||
| VREFDQ | Reference Voltage for DQ | ||
| VSS | Ground | ||
| VSSQ | DQ | Ground | |
| ZQ | Reference Pin for ZQ calibration |
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