AlteraUnited States

EPF10K50VRI240-4

FPGAs (Field Programmable Gate Array)RQFP

Altera FLEX 10K embedded PLD, EPF10K50V features 2,880 logic elements, 20,480 RAM bits, 3.3V core voltage, industrial temperature range, and JTAG boundary scan support.Checked against the datasheet

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Technical parameters

Key specs

Logic elements2 ~ 880
I/O count310
Core voltage3 ~ 3.6 V

Datasheet-verified parameters

27 items
ParameterValue and test conditionsSource
Logic elements (LEs)2,880
Maximum user I/O pins310
Total RAM bits20,480
Supply voltage for internal logic and input buffersMin: 3.00 V, Max: 3.60 V
PackageRQFP, BGA
Ambient temperatureFor industrial use: Min: -40 °C, Max: 85 °C
Temperature GradeIndustrial
Recommended Operating Conditions VCCINTMin: 3.00 V, Max: 3.60 V
Recommended Operating Conditions VCCIOMin: 3.00 V, Max: 3.60 V
Absolute Maximum Ratings Supply voltageMin: -0.5 V, Max: 4.6 V
Absolute Maximum Ratings DC input voltageMin: -2.0 V, Max: 5.75 V
Absolute Maximum Ratings Junction temperatureMax: 135 °C (RQFP and BGA packages)
High-level input voltageMin: 2.0 V, Max: 5.75 V
Low-level input voltageMin: -0.5 V, Max: 0.8 V
High-level output voltageMin: 2.4 V (TTL, IOH = -8 mA DC), Min: VCCIO - 0.2 V (CMOS, IOH = -0.1 mA DC)
Low-level output voltageMax: 0.45 V (TTL, IOL = 8 mA DC), Max: 0.2 V (CMOS, IOL = 0.1 mA DC)
Input pin leakage currentMin: -10 μA, Max: 10 μA (VI = 5.3 V to -0.3 V)
Tri-stated I/O pin leakage currentMin: -10 μA, Max: 10 μA (VO = 5.3 V to -0.3 V)
VCC supply current (standby)Typ: 0.3 mA, Max: 10 mA (VI = ground, no load)
Input capacitanceMax: 10 pF (VIN = 0 V, f = 1.0 MHz)
Input capacitance on dedicated clock pinMax: 15 pF (VIN = 0 V, f = 1.0 MHz)
Output capacitanceMax: 10 pF (VOUT = 0 V, f = 1.0 MHz)
Typical gates (logic and RAM)50,000
Maximum system gates116,000
Embedded array blocks (EABs)10
Logic array blocks (LABs)360
JTAG Boundary-ScanCompliant with IEEE Std. 1149.1-1990

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