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LMK00304SQ

CLOCK BUFFER 4-OUT 3GHZ 32WQFN

LMK00304 is a 3-GHz 4-output differential ultra-low additive jitter clock buffer/level translator in a 32-lead WQFN package, supporting LVPECL, LVDS, and HCSL outputs with an operating temperature range of -40°C to +85°C.Checked against the datasheet

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Technical parameters

Key specs

Max frequency3.1 GHzMax · 3.1 GHz (Vcco = 3.3 V ± 5%，RT = 160 Ω to GND，VOD ≥ 400 mV)

Outputs4

Supply voltage3.15 ~ 3.45 V

Datasheet-verified parameters

16 items

Parameter	Value and test conditions	Source
Maximum Output Frequency	3.1 GHz (Vcco = 3.3 V ± 5%, RT = 160 Ω to GND, VOD ≥ 400 mV)
Number of Outputs	4 Differential Outputs (2 Banks with 2 each) + 1 LVCMOS Output
Supply Voltage	VCC: 3.15 V to 3.45 V; VCCO: 2.5 V ± 5% or 3.3 V ± 5%
Package	WQFN (32) 5.00 mm × 5.00 mm
Operating Temperature	-40 °C to +85 °C
Grade	Industrial
RoHS	Yes
Recommended Operating Conditions	TA: -40 °C to 85 °C; TJ: Max 125 °C; VCC: 3.15 V to 3.45 V; VCCO: 2.5 V ± 5% or 3.3 V ± 5%
Absolute Maximum Ratings	VCC, VCCO: -0.3 V to 3.6 V; TSTG: -65 °C to +150 °C; TJ: Max +150 °C
Additive RMS Jitter	20 fs RMS (10 kHz to 1 MHz) with LMK03806 source at 156.25 MHz
Power Supply Rejection Ratio (PSRR)	-65 / -76 dBc (LVPECL/LVDS) at 156.25 MHz
Input Types	LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or Single-Ended Clocks
Output Types	LVPECL, LVDS, HCSL, or Hi-Z (Selectable)
ESD Protection	HBM: ±2000 V; CDM: ±750 V
Storage Temperature	-65 °C to +150 °C
Junction Temperature	Max 125 °C (Recommended), Max 150 °C (Absolute)

All parameters (7)ExpandCollapse

Power
Core Supply Voltage Range	3.15 V (Min) to 3.45 V (Max)
Output Supply Voltage Range	3.3 V ± 5% or 2.5 V ± 5%
AC and DC characteristics
PSRR	-65 / -76 dBc (LVPECL/LVDS) at 156.25 MHz
Environment and package
Ambient Temperature Range	-40 °C to 85 °C
Body Size (NOM)	5.00 mm × 5.00 mm
Package	WQFN (32)
Other
LVPECL Additive Jitter	20 fs RMS (10 kHz to 1 MHz)

Pinout and package

PackageWQFN (32) 5.00 mm × 5.00 mm

Pin	Name	Function
11		OSCin (Crystal Input)
12		OSCout (Crystal Output)
25	NC	(Not Connected)
29		REFout (LVCMOS Reference Output)
30	VCCOC	(REFout Power Supply)
31		REFout_EN (REFout Enable)
1, 8, 17, 24	GND	(Ground)
10, 28	VCC	(Core Power Supply)
13, 16		CLKin_SEL0, CLKin_SEL1 (Clock Input Selection)
14, 15		CLKin0, CLKin0* (Universal Clock Input 0)
18, 19		CLKoutB1*, CLKoutB1 (Differential Clock Output B1)
2, 5	VCCOA	(Bank A Output Power Supply)
20, 23	VCCOB	(Bank B Output Power Supply)
21, 22		CLKoutB0*, CLKoutB0 (Differential Clock Output B0)
26, 27		CLKin1*, CLKin1 (Universal Clock Input 1)
3, 4		CLKoutA0, CLKoutA0* (Differential Clock Output A0)
6, 7		CLKoutA1, CLKoutA1* (Differential Clock Output A1)
9, 32		CLKout_TYPE0, CLKout_TYPE1 (Output Type Selection)
DAP	DAP	(Die Attach Pad / Ground)

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DatasheetDatasheet · 2.0 MB · 2026-10-29

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