Figure 4-1. RGY PACKAGE, QFN-2…
Texas InstrumentsUnited States
CTRL BUCK SYNC PWM 4.5V-60V 20-VQFN
TPS40170 is a 4.5-V to 60-V wide-input synchronous PWM buck controller with a switching frequency of 100 kHz to 600 kHz, in a 20-pin VQFN package, featuring programmable UVLO, overcurrent protection, and bidirectional synchronization.Checked against the datasheet
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Technical parameters
Key specs
TopologyBuck
Outputs1
Input voltage4.5 ~ 60 V
Switching frequency100 ~ 600 kHz
Datasheet-verified parameters
20 items| Parameter | Value and test conditions | Source |
|---|---|---|
| Topology | Synchronous PWM Buck | |
| Outputs | 1 | |
| Input Voltage Range | 4.5 V to 60 V | |
| Switching Frequency | 100 kHz to 600 kHz | |
| Package | VQFN, 20 pins, 4.50 mm × 3.50 mm | |
| Operating Temperature | -40 °C to 125 °C |
All parameters (6)
| Power | |
|---|---|
| Input voltage | 4.5 V to 60 V |
| Reference voltage | 600 mV |
| AC and DC characteristics | |
| Switching frequency | 100 kHz to 600 kHz |
| Environment and package | |
| Operating junction temperature | -40 °C to 125 °C |
| Package | 20-Pin 3.5 mm × 4.5 mm VQFN (RGY) |
| Thermal shutdown | 165°C |
Pinout and package
Figure 4-1. RGY PACKAGE, QFN-2…
| Pin | Name | Function | Source |
|---|---|---|---|
| 1 | ENABLE, Enable pin, active high, low level enters low-power shutdown mode | ||
| 2 | SYNC, Synchronization pin, bi-directional, for frequency synchronization | ||
| 3 | M/S, Primary/Secondary mode selector pin, for frequency synchronization mode selection | ||
| 4 | RT, Oscillator frequency setting pin, sets switching frequency via resistor | ||
| 5 | SS, Soft-start pin, sets soft-start time via capacitor | ||
| 6 | TRK, Voltage tracking pin, for output voltage tracking | ||
| 7 | FB, Feedback pin, negative input to error amplifier | ||
| 8 | COMP, Error amplifier output pin, connects compensation network | ||
| 9 | AGND, Analog ground pin | ||
| 10 | VDD, 3.3V regulated output pin | ||
| 11 | PGOOD, Power good indicator pin, open-drain output | ||
| 12 | ILIM, Overcurrent limit setting pin | ||
| 13 | PGND, Power ground pin | ||
| 14 | LDRV, Low-side FET gate driver output pin | ||
| 15 | VBP, 8V regulated output pin, for gate driver | ||
| 16 | SW, Switching node pin, connects to synchronous buck converter switching node | ||
| 17 | HDRV, High-side FET gate driver output pin | ||
| 18 | BOOT, Bootstrap capacitor node pin, for high-side FET gate driver | ||
| 19 | VIN, Input voltage pin | ||
| 20 | UVLO, Undervoltage lockout pin, sets UVLO threshold |
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