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Technical parameters

Key specs

Max frequency20 GHzMax
Outputs2
Supply voltage3.15 ~ 3.45 V

Datasheet-verified parameters

19 items
ParameterValue and test conditionsSource
Maximum Output Frequency20 GHz
Number of Outputs2 (Differential Output A and B)
Supply Voltage3.15 V to 3.45 V (Typ 3.3 V)
PackageVQFN (40), 6.00mm × 6.00mm
Operating Temperature-40°C to 85°C
RoHSYes
Recommended Operating ConditionsVCC: 3.15 V to 3.45 V, TA: -40°C to 85°C
Absolute Maximum RatingsVCC: -0.3 V to 3.6 V, TJ: -40°C to 150°C, Tstg: -65°C to 150°C
Supply Current340 mA (Typ, fOUT=14 GHz, pOUT=3 dBm)
Single-ended Output Power2 dBm (Typ, fOUT=15 GHz, 50-Ω pullup)
Reference Input Frequency5 MHz to 1400 MHz (OSC_2X=0)
Reference Input Voltage0.2 Vpp to 2 Vpp
Phase Detector Frequency5 MHz to 300 MHz (Fractional mode, MASH_ORDER=1,2,3)
Charge Pump Current3 mA to 15 mA (CPG=4 to 7)
Normalized PLL 1/f Noise-129 dBc/Hz (Typ, fPD=100 MHz, fVCO=12 GHz)
Normalized PLL Noise Floor-236 dBc/Hz (Typ, fPD=100 MHz, fVCO=12 GHz)
VCO Doubler Output Range15 GHz to 20 GHz (DBLR_IBIAS_CTRL1=3115)
ESD Rating±2000 V (HBM), ±750 V (CDM)
Storage Temperature-65°C to 150°C

Pinout and package

5 Pin Configuration and Functi…
5 Pin Configuration and Functi…
Package: VQFN (40), 6.00mm × 6.00mm
PinNameFunctionSource
1CE, Chip enable input, Active HIGH
3VbiasVCO, VCO bias, requires 10-μF capacitor to VCO ground
5SYNC, Phase synchronization pin, programmable threshold
7VccDIG, Digital supply, bypass to digital ground recommended
8OSCinP, Reference input clock (+), high-impedance self-biasing, AC-coupling capacitor required
9OSCinM, Reference input clock (-), high-impedance self-biasing, AC-coupling capacitor required
10VregIN, Input reference path regulator output, requires 1-μF capacitor to ground
11VccCP, Charge pump supply, bypass to charge pump ground recommended
12CPout, Charge pump output, connect loop filter C1 recommended
13GND, Charge pump ground
15VccMASH, Digital supply, bypass to digital ground recommended
16SCK, SPI clock, high impedance CMOS input, 1.8-V to 3.3-V logic
17SDI, SPI data, high impedance CMOS input, 1.8-V to 3.3-V logic
18RFoutBM, Differential output B (-), 50-Ω pullup to Vcc required, can be used as SYSREF output
19RFoutBP, Differential output B (+), 50-Ω pullup to Vcc required, can be used as SYSREF output
20MUXout, Multiplexed output pin — lock detect, readback, diagnostics, ramp status
21VccBUF, Output buffer supply, bypass to RFout ground recommended
22RFoutAM, Differential output A (-), 50-Ω pullup to Vcc required
23RFoutAP, Differential output A (+), 50-Ω pullup to Vcc required
24CSB, SPI latch, Chip Select Bar, high-impedance CMOS input, 1.8-V to 3.3-V logic
26VccVCO2, VCO supply, bypass to VCO ground recommended
27VbiasVCO2, VCO bias, requires 1-μF capacitor to VCO ground
28SysRefReq, SYSREF request input for JESD204B support
29VrefVCO2, VCO supply reference, requires 10-μF capacitor to VCO ground
30RampClk, Input pin for ramping mode, can be used to clock the ramp in manual ramping mode or as a trigger input
32RampDir, Input pin for ramping mode, can be used to change ramp direction in manual ramping mode or as a trigger input
33VbiasVARAC, VCO Varactor bias, requires 10-μF capacitor to VCO ground
35Vtune, VCO tuning voltage input
36VrefVCO, VCO supply reference, requires 10-μF capacitor to VCO ground
37VccVCO, VCO supply, bypass to ground recommended
38VregVCO, VCO regulator node, requires 1-μF capacitor to ground
2, 4, 25, 31, 34, 39GND, VCO ground
6, 14GND, Digital ground
DAPGND, Die Attached Pad, used for RFout ground

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