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Clock Data Recovery (CDR)

The MAX3675 is a complete clock-recovery and data-retiming IC incorporating a limiting amplifier. It is intended for 622Mbps SDH/SONET applications and operates from a single +3.3V supply. The MAX3675 has two differential input amplifiers: one accepts PECL levels, while the other accepts small-signal analog levels. The analog inputs access the limiting amplifier stage, which provides both a received-signal-strength indicator (RSSI) and a programmable-threshold loss-of-power (LOP) monitor. Selecting the PECL amplifier disables the limiting amplifier, conserving power. A loss-of-lock (LOL) monitor is also incorporated as part of the fully integrated PLL. Applications Add/Drop Multiplexers ATM Switches Digital Cross-Connects SDH/SONET Access Nodes SDH/SONET Transmission Systems

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Application Specific Clock/Timing

CLOCK-RECOVERY AND DATA-RETIMING

Application Specific Clock/Timing

622 MEGA BIT PER SEC, LOW-POWER,

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